1. Field of the Invention
This invention relates generally to a current generating (dynamic element matching) circuit, and more particularly to such a current generating circuit which is suitable for use in current switching for a digital-to-analog (D/A) converter.
2. Description of the Prior Art
First, a previously proposed current generating circuit 4, disclosed in Japanese Patent Publication No. 54-24098, will hereinafter be explained with reference to FIG. 1.
The current generating circuit 4 comprises a current dividing circuit 3 in a current mirror configuration which is formed of transistors Q.sub.1 and Q.sub.2. Currents I.sub.1 and I.sub.2 passing through the transistors Q.sub.1 and Q.sub.2 are respectively obtained by dividing a current 2I substantially by two, so that the currents I.sub.1 and I.sub.2 are substantially equal to each other. A pair of differential switching circuits 1a and 1b, which form a current change-over circuit 2, respectively switch and deliver the currents I.sub.1 and I.sub.2 alternately to a pair of output terminals T.sub.3 and T.sub.4. The differential switching circuit 1a is formed of a pair of transistors Q.sub.3 and Q.sub.4 which have their emitters connected with each other, and their connecting point is connected with the collector and the base of the transistor Q.sub.1. The other differential switching circuit lb is formed of a pair of transistors Q.sub.5 and Q.sub.6 which have their emitters connected with each other, and their connecting point is connected with the collector of the transistor Q.sub.2.
The collectors of the transistors Q.sub.3 and Q.sub.5 are connected to the output terminal T.sub.3 in common, while the collectors of the transistors Q.sub.4 and Q.sub.6 are to the other output terminal T.sub.4 in common. The output terminals T.sub.3 and T.sub.4 are grounded respectively through capacitors Cx and Cy constituting low pass filters.
The input terminals T.sub.1 and T.sub.2, for switching, are fed with a pair of opposite-phased switching signals E.sub.1 and E.sub.2 with a predetermined frequency. The switching input terminal T.sub.1 is connected to the bases of the transistors Q.sub.3 and Q.sub.6 in common, while the other switching input terminal T.sub.2 is connected to the bases of the transistors Q.sub.4 and Q.sub.5 in common.
Next, the operation of the current generating circuit 4 will be explained. When the switching signal E.sub.1 supplied to the input terminal T.sub.1 is at a high level, the switching signal E.sub.2 supplied to the input terminal T.sub.2 is at a low level, so that the transistors Q.sub.3 and Q.sub.6 are turned on while the transistors Q.sub.4 and Q.sub.5 are turned off. Therefore, the current I.sub.1 from the current dividing circuit 3 is delivered to the terminal T.sub.3 and the current I.sub.2 is delivered to the terminal T.sub.4, respectively.
When the switching signal E.sub.2 supplied to the switching input terminal T.sub.2 is at the high level, the switching signal E.sub.1 supplied to the input terminal T.sub.1 is at the low level, so that the transistors Q.sub.4 and Q.sub.5 are turned on while the transistors Q.sub.3 and Q.sub.6 are turned off. Therefore, the current I.sub.1 from the current dividing circuit 3 is delivered to the terminal T.sub.4 and the current I.sub.2 is delivered to the terminal T.sub.3, respectively.
Thus, the output terminal T.sub.3 is alternately fed with the currents I.sub.1 and I.sub.2, while the output terminal T.sub.4 is alternately fed with the currents I.sub.2 and I.sub.1. These currents I.sub.2 and I.sub.1 are averaged by the capacitors Cx and Cy constituting the low pass filters, so that both of the output terminals T.sub.3 and T4 are equally fed with a current I (I=(I.sub.1 +I.sub.2)/2), as a result. In other words, the current generating circuit 4 can provide at its two output terminals the output current I which is derived by accurately dividing the input current 2I supplied thereto by two.
Let it now be assumed that the current generating circuits 4a, 4b and 4c, each being explained with reference to FIG. 1 as disclosed in Japanese Patent Publication No. 54-24098, are connected upward in a piling manner as shown in FIG. 2. The current generating circuit 4a at the first stage is disposed to divide the input current 2I by two to obtain the two output currents, I and I, one of which is delivered to the output terminal T.sub.4, and the other of which is supplied to one input terminal of the current generating circuit 4b at the next stage.
Then, the current generating circuit 4b is disposed to divide the input current I by two to obtain two output currents I/2 and I/2 , one of which is outputted to an output terminal T.sub.5, and the other of which is supplied to one input terminal of the current generating circuit 4c at the third stage.
By repeating the above operation, the current generating circuit 4c at the third stage derives a current I/4 at its output terminal T.sub.6. Incidentally, reference letters T.sub.3, T.sub.3 ' and T.sub.3 " designate the other output terminals of the current generating circuits 4a, 4b and 4c, respectively.
If each of the output currents delivered to the output terminals T.sub.4, T.sub.5 and T.sub.6 are controlled independently by different switches which are turned on and off in accordance with binary combinations of a 3-bit digital signal, a current generator type D/A converter can be formed.
The current generating circuit 4 shown in FIG. 1 can derive the substantially equal current at the output terminals T.sub.3 and T.sub.4 by averaging the input currents I.sub.1 and I.sub.2 supplied to the differential type switching circuits 1a and lb. However, if the current generating circuits are arranged in multi-stage as shown in FIG. 2, to form e.g. an n-bit D/A converter, the total number of the transistors Q.sub.3 and Q.sub.4, for example, in the differential switching circuit la is increased by n times, so that the voltage necessary to operate all these transistors Q.sub.3 and Q.sub.4 or the like becomes higher as the bit number of the D/A converter is increased.
To solve the above-mentioned problem, Japanese Patent Publication No. 57-31809 discloses to derive from the single current generating circuit 4 the output currents I, I/2, I/4 . . . which have been delivered one by one from the current generating circuits 4a, 4b, 4c . . . That is, the single current generating circuit provided with a plurality of output terminals for deriving a plurality of output currents, for example I and I/2, is disclosed. The construction shown in this document can reduce the number of the current generating circuits 4a, 4b, 4c . . . which are piled by connecting in multiple stages, as shown in FIG. 2, thereby making it possible to reduce the source voltage.
A single-stage current generating circuit equivalent to the above-mentioned two-stage current generating circuit and the operating waveforms thereof is explained below with reference to FIGS. 3 and 4, by using the principle of Japanese Patent Publication No. 57-31809.
In FIG. 3, reference numeral 4 designates an overall current generating circuit in which an input terminal T.sub.15 is connected e.g. to a current generating circuit for the upper digit, and an output terminal T.sub.14 to a current generating circuit for the lower digit, in a manner that they are piled in multiple stages, similarly to FIG. 2. The current dividing circuit 3 is formed of a current-mirror circuit comprising transistors Q.sub.11, Q.sub.12, Q.sub.13 and Q.sub.14, for dividing an input current I supplied to the input terminal T.sub.15 substantially equally by four. That is, the input current is divided into 2.sup.n (n=2, 3, 4 . . .). The collectors of the transistors Q.sub.11 to Q.sub.14 are connected to switching circuits 11, 12, 13 and 14, respectively, while the bases and the emitters thereof are respectively connected in common. The base of the transistor Q.sub.11 is connected to the collector of the same. The switching circuits 11, 12, 13 and 14 are respectively formed of switching transistors Q.sub.15 to Q.sub.18, Q.sub.19 to Q.sub.22, Q.sub.23 to Q.sub.26 and Q.sub.27 to Q.sub.30. The emitters of the transistors Q.sub.15 to Q.sub.18, Q.sub.19 to Q.sub.22, Q.sub.23 to Q.sub.26 and Q.sub.27 to Q.sub.30 comprised in the switching circuits 11, 12, 13 and 14 are respectively connected in common. A control terminal T.sub.10 is connected to the respective bases of the transistors Q.sub.15, Q.sub.19, Q.sub.23 and Q.sub.27, while a control terminal T.sub.11 is connected to the respective bases of the transistors Q.sub.16, Q.sub.20, Q.sub.24 and Q.sub.28. Further, a control terminal T.sub.12 is connected to the respective bases of the transistors Q.sub.17, Q.sub.21, Q.sub.25 and Q.sub.29, while a control terminal T.sub.13 is connected to the respective bases of the transistors Q.sub.18, Q.sub.22, Q.sub.26 and Q.sub.30. The collectors of the transistors Q.sub.15, Q.sub.20, Q.sub.25 and Q.sub.30 arranged in the switching circuits 11 to 14 are connected in common to a first output terminal T.sub.16. A capacitor C.sub.1 forming a low pass filter is interposed between the first output terminal T.sub.16 and ground. In the same manner, the collectors of the transistors Q.sub.16, Q.sub.21, Q.sub.26, Q.sub.27 and Q.sub.30 are connected in common to the output terminal T.sub.16. Further, the collectors of the transistors Q.sub.17, Q.sub.22, Q.sub.23 and Q.sub.28 are connected in common to a second output terminal T.sub.17. A capacitor C.sub.2 forming a low pass filter is interposed between the second output terminal T.sub.17 and ground. Further in the same manner, the collectors of the transistors Q.sub.18, Q.sub.19, Q.sub.24 and Q.sub.29 are connected in common to the output terminal T.sub.14 `which leads to the current generating circuit for the lower digit. A capacitor C.sub.3 forming a low pass filter is interposed between the output terminal T.sub.14 and ground.
In the construction shown in FIG. 3, the control terminals T.sub.10 to T.sub.13 are respectively supplied with control pulses A.sub.1 to A.sub.4 as shown in FIG. 4. For example, when the control terminal T.sub.10 is supplied with the pulse A.sub.1, the transistors Q.sub.15, Q.sub.19, Q.sub.23 and Q.sub.27 are turned on and maintain the "on" condition as long as the pulse A.sub.1 is at the high level, so that a current flows in the direction indicated by the arrow. The same operation is carried out with the pulses A.sub.2 to A.sub.4. When the current I is fed to the input terminal T.sub.15, the current I/2 is derived at the first output terminal T.sub.16 and the current I/4 is derived at the second output terminal T.sub.17 and the terminal T.sub.14.
With the circuit construction of FIG. 3 as described above, while the control terminals T.sub.10 to T.sub.13 are respectively applied with the pulsed A.sub.1 to A.sub.4 for one cyclic period thereof, the switching circuit 11 has the transistors Q.sub.15 and Q.sub.16, connected to the output terminal T.sub.16 in common, turned on to flow the current to the transistor Q.sub.11 arranged in the current dividing circuit 3. The switching circuit 12, in the same manner, has the transistors Q.sub.20 and Q.sub.21 turned on to flow the current to the transistor Q.sub.12 in the current dividing circuit 3, the switching circuit 13 also has the transistor Q.sub.25 and Q.sub.26 turned on to flow the current to the transistor Q.sub.13 in the current dividing circuit 3, and the switching circuit 14 has the transistors Q.sub.27 and Q.sub.30 turned on to flow the current to the transistor Q.sub.14 of the current dividing circuit 3. Thus, if the number of the transistors arranged in the current dividing circuit 3 (the current source are increased to 2, 4, 8, 16 . . . 2.sub.n, or if the number of the processed bits (output derived at the output terminals T.sub.16 and T.sub.17) taken out from each of the current generating circuits 4a, 4b . . . connected in the piling manner as shown in FIG. 2 are increased to 1, 2, 3 ... n, the number of transistors in the switching circuits 11 to 14 for turning on and off each of the transistors in the current dividing circuit 3 is correspondingly increased to 2, 4, 8 . . .2.sub.n. Particularly, for realizing a highly accurate D/A converter the number of necessary transistors becomes inacceptably immense.
Further, the current change-over circuit 2 formed of the differential switches 1a and 1b shown in FIG. 1 presents another disadvantage in that the emitter currents of the respective transistors Q.sub.3 to Q.sub.6 thereof do not wholly flow to their collectors but the collector current is only, .beta./(1+.beta.), a portion of the emitter current and the rest, 1/(1+.beta.), of the same flows to the base. In other words, the output currents delivered to the output terminals T.sub.3 and T.sub.4 are reduced by 1/(1+.beta.) from (I.sub.1 +I.sub.2)/2. Accordingly, if the current generating circuits of FIG. 1 are connected in multiple stages as shown in FIG. 2, the error in the output current becomes larger in further succeeding stages, so that if it is used as the aforementioned current source type D/A converter, there will be produced a large conversion error.
This problem can be solved by constructing the transistors Q.sub.3 to Q.sub.6 of the differential switching circuits la and lb in the current change-over circuit 2 shown in FIG. 1 in a Darlington configuration to thereby make the .beta. factor substantially large.
FIG. 5 illustrates a circuit in which the differential switching circuit la, for example, of the current change-over circuit 2 in FIG. 1 is formed in a Darlington configuration. In this example, the transistor circuit Q.sub.3 is formed of a pair of Darlington-connected transistors Q.sub.3a and Q.sub.3b, and the transistor circuit Q.sub.4 is formed of a pair of Darlington-connected transistors Q.sub.4a and Q.sub.4b. Specifically, the emitter of the transistor Q.sub.3b is connected to the base of the transistor Q.sub.3a, while the collector of the transistor Q.sub.3a is connected to the collector of the transistor Q.sub.3b. The emitter of the transistor Q.sub.4b is connected to the base of the transistor Q.sub.4a, while the collector of the transistor Q.sub.4a is connected to the collector of the transistor Q.sub.4b.
Assuming that the factors .beta. of the transistors Q.sub.3a to Q.sub.4b are equal, the current flowing to the bases of the respective transistors Q.sub.3b and Q.sub.4b is represented by I.sub.1 /(1+.beta.).sup.2. It is therefore understood that the accuracy of the output current for the input current is improved.
However, such a configuration causes a minimal operating voltage at the output terminals T.sub.3 and T.sub.4, on the basis of the common emitter of the transistors Q.sub.3a and Q.sub.4a, to be twice the base-emitter voltage V.sub.BE of the transistors Q.sub.3a to Q.sub.4b, that is, 2V.sub.BE. Therefore, if the current generating circuits are connected in multiple stages as shown in FIG. 2, the minimal operating voltage for the current generating circuit at the highest stage will be four times the value 2V.sub.BE. Thus, as the number of stages is increased, the minimal operating voltage thereof is largely elevated.